Mobile Industry Processor Interface (MIPI®) Alliance C-PHY® is a high-speed serial interface specification to provide high throughput performance over bandwidth limited channels for connecting to peripherals, including displays and cameras. C-PHY® interface is based on 3-phase symbol encoding technology for delivering high bits per symbol (e.g., 2.28 bits per symbol) over three wire trios.
C-PHY® interface was proposed to increase the efficiency of data rate by encoding and decoding the data using three states of wires (high, mid, and low). C-PHY® interface offers the advantage of jitter tracking since the clock is embedded in every cycle of data transaction. However, there is a significant disadvantage when it comes to the design implementation of C-PHY® interface. For example, skews in the signals delivered over the three wires may cause timing violation using traditional clock recovery circuits when recovering clock embedded in the signals.